Reducing power consumption in wireless equipment is of high importance. This is especially true for the complex equipment required to receive high data rate channels, such as, for example, third generation partnership project high speed downlink packet access (3GPP HSDPA) channels. There are several known techniques for reducing power consumption in integrated circuits. These include clock gating and power supply disconnection.
Well-known techniques of clock gating are discussed, for example, in the paper by Tellez et al. entitled “Activity-Driven Clock Design for Low Power Circuits” as published in the ICCAD-95 Digest of Technical Papers at pages 62-65. Activity-driven clock trees reduce the dynamic power consumption of synchronous digital complementary metal oxide semiconductor (CMOS) circuits. Sections of an activity-driven clock tree can be turned on/off by gating the clock signals during the active/idle times of the clock elements. The goal is to minimize the dynamic power consumption of a system.
Well-known techniques of power supply disconnection are described, for example, in the paper of Mutoh et al. entitled “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS” as presented in the IEEE Journal of Solid-State Circuits, volume 30, at pages 847-854 in August 1995. Multithreshold-voltage CMOS circuit technology is described therein, exhibiting one-volt supply voltage, high-speed, low-power, large scale integration (LSI) operation. Metal oxide semiconductor field effect transistors (MOSFETs) with two different threshold voltages are employed on a single chip, and a sleep control scheme is utilized for efficient power management.
While the generic power reduction techniques of clock gating and power supply disconnection (power supply gating) are effective, prior art techniques do not adequately address the question of when such gating should occur.
Accordingly, it would be desirable to overcome the disadvantages associated with prior art techniques.